The invention relates generally to a pre-erasing/erasing mechanism for flash EEPROM (Electrically Erasable and Programmable Read Only Memory) devices. The invention is particularly useful for flash arrays that utilize Negative Gate Channel Erase (NGCE) operations because it improves erase operations by reducing field intensity variations in tunnel oxides caused by processing deviations, increases the number of endurance cycles, and results in fewer over-erase errors.
The endurance cycles of an EEPROM, especially the number of program and erase cycles, is the primary determinant of the life span of such device. Endurance cycles refer to the number of times which data can be reliably erased, re-programmed, and read back without errors. Accordingly, the number of endurance cycles dictates in large part the usable life of an EEPROM device. Consequently, one significant goal of prior art efforts is the maximization of such endurance cycles through the use of improved cell architectures which minimize cycle stress, as well as intelligent erase, program methods designed to be less stressful on the cell architecture.
Fowler-Nordheim (FN) tunneling is one of the most well-known, well-understood and prevalent techniques used in the art for erasing flash memory cells. A significant problem arises from the fact that certain cells (bits) in the memory array tend to be xe2x80x9cfastxe2x80x9d and others xe2x80x9cslowxe2x80x9d during an erase operation. In other words, because such cells tend to over-accumulate, or under-accumulate charge on their floating gates, or because charge becomes trapped in various locations, these cells tend to have threshold voltages that deviate significantly from a target threshold voltage. For this reason, when a xe2x80x9cfastxe2x80x9d cell is erased, it is much more likely to become over-erased. When a cell is over-erased during an erase operation, this causes additional administrative overhead, because it must be corrected if at all possible. This is undesirable, of course, because it slows down the operation of the device from being re-programmed with new data.
The existence of excess charge on the xe2x80x9cfastxe2x80x9d bits caused them to be over-erased for a couple of reasons. First, the FN erase mechanism depends strongly on the electrical field across the thin tunnel oxide layer in the flash cell; with more charge, the field is proportionately higher. This causes more charge to move off the floating gate during the erase operation. In other words, the fast bits have electrical field intensities that deviate significantly from desired target field strengths. Second, at the beginning of the FN erase, the floating gates are fully charged (i.e., in a programmed state) and the electrical field is a maximum. This means that the rate of erasure (the electrical discharge rate of the floating gate) is also highest at the onset of the FN erase operation. Thus, if fast bits are not corrected, they tend to become over-erased, and this leads to concomitant problems of excess leakage current and/or data errors. In the long run, these leaky bits cause failures, reduce endurance cycles, etc. As mentioned above, the problem is especially acute in (but not limited to) FN tunneling erase operations used with NGCE configurations. This is because the electrical field becomes extremely strong between the negative gate and the substrate well.
To date, there are very few practical solutions for dealing with this phenomenon, and no easy way known to applicants for compensating for electrical field intensity variations that occur in flash memory cell arrays. These field variations arise naturally both from wafer processing operations, which, by their nature, result in differences in cell structures, tunnel oxide characteristics (thickness and uniformity), etc., as well as from cycling of the device in normal operation. As the number of cells increase in EEPROM devices, and integration density increases, and cycling increases, the field variations also correspondingly increase because of the nature of normal distributions.
A related situation is addressed by U.S. Pat. No. 5,901,089, incorporated by reference herein. In this reference, the individual logic levels of a multi-bit cell are kept stable by ensuring that the threshold voltages of such cell are maintained within predefined threshold ranges. This is accomplished using what it refers to as xe2x80x9cminixe2x80x9d erase/program operations, where a pulse is applied so that only enough charge is added or removed from a cell sufficient to keep it within a safe operating range for that state. While this approach is beneficial for improving sensing (read) operations, this technique does not appear to be very practical as a pre-erase conditioning operation. This is because it requires a significant amount of administrative overhead to perform this type of procedure on a cell by cell basis. Moreover, the reference is primarily directed ensuring that Vt overshoot is reduced for each programmed cell, and does not really address the issue of how to ensure that the behavior of cells collectively is relatively uniform and predictable during a subsequent operation in which they are to be transitioned from one logical level to another. In other words, there is no attempt made to treat one segment of the cell population (the xe2x80x9cfastxe2x80x9d cells) differently than another as may be necessary to achieve better operational results. Nor does this reference teach or suggest using a series of lesser strength erase signals to completely erase a programmed cell.
For these reasons, an effective method for dealing with so called fast bits is not known in the art, but is extremely desirable. Optimally, the erased set of cells has a relatively uniform distribution centered around a target erase value. To get this uniform distribution, however, it is necessary: (1) to place the cells in a similar state (initial floating gate voltage/electrical field); and (2) for them to have similar electrical discharge characteristics. The first step can be accomplished by a conventional programming step, which, in theory, is intended to add sufficient charge to put all the cells into an initial target programmed voltage threshold state Vp. To date, nonetheless, applicants are unaware of specific and practical mechanisms for achieving the second step of controlling individual cell electrical discharge characteristics. To accomplish this goal, it is necessary to control the initial electric field at the tunneling oxide. If this electric field is not reduced at the onset of FN erasure for the fast bit segment of the array, the fast bits will be erased faster than average bits in the memory array. By the time the average bits are erased, the fast bits are already in a state of over-erasure. Correspondingly, if the electric field can be reduced at the beginning of the erasure for a particular bit, this will slow down the rate of erasure for the bit in question.
An object of the present invention, therefore, is to eliminate the problems generally inherent in the aforementioned FN tunneling erase operations when used with NGCE type EEPROM devices;
Another object of the present invention is to provide an improved circuit and method for erasing flash memory cells so that threshold voltage distributions of such cells are tightened both before and after an erase operation;
A further object of the present invention is to provide a circuit and method for pre-erasing flash memory cells with a conditioning signal to adjust and equalize their threshold voltage distributions prior to an erase operation;
A related object of the present invention is to provide a circuit and method for generating such conditioning signal, so that threshold voltage distributions can be finely controlled by a series of conditioning signals having predetermined magnitudes, durations, and similar signal characteristics;
Another object of the present invention is to provide that such conditioning signals can be custom tailored based on the particular processing implementation for such memory cell array, or, alternatively, that such signals can be determined in the field during normal operation of a flash EEPROM device;
Yet another object of the present invention is to control and equalize electrical field intensities across a tunneling oxide for flash memory cells in a memory array, and to compensate for normal manufacturing variations causing such field intensity deviations;
A related object of the present invention, is to reduce a discharge rate of fast bits in a flash memory cell to make such fast bits discharge at a rate comparable to a an average flash memory cell having a desired discharge rate;
Another related object of the present invention is to reduce the probability of a fast bit from becoming over-erased, by conditioning such bit to have an electrical field comparable to that of an average flash memory cell prior to an erase operation, so that such fast bit behaves essentially like an average memory cell during such erase operation, and is therefore not over-erased by a full strength erase pulse; and
Another object of the present invention is to identify fast bits in a flash memory array and provide them with conditioning signals which modify erase behavior of such fast bits but not erase characteristics of average or slow bits in such array;
A related object of the present invention is to provide an erase mechanism that uses a stepped or graduated reduction of charge for cells in a flash memory, so that erase cycles and resulting erased voltage distributions are more accurately controlled;
Yet a further related object is to reduce cell leakage current by eliminating the occurrences of over-erased fast memory bits in a flash memory array;
Still another object of the present invention is to provide a memory cell array capable of longer life span, by increasing the number of endurance cycles;
An additional object of the present invention is to reduce the possibility of malfunctions and errors in flash memory cells caused by excessive numbers of leaky data bits.
Yet still another objective of the present invention is to provide a complete integrated circuit that implements the aforementioned methods.
Another objective of the present invention is to provide an improved erase circuit for accomplishing both the regular full strength Negative Gate Channel Erase and pre-erase operations described above, using the same charge pump.
A further object of the present invention is to provide a programmed logic controller for achieving step-by-step time sequencing of varying intensity conditioning signals to effectively reduce the electrical field across the tunneling oxide at the initial phase of erasure in order to control/equalize the discharge rate of fast bits in Flash memory array.
These objectives and other significant advantages are provided by the novel methods and circuits disclosed herein. A method of slowing down erase speeds of xe2x80x9cfastxe2x80x9d discharge flash cells in a memory arrayxe2x80x94where the fast discharge flash cells are generally characterized by erase speeds substantially faster than target erase speeds for flash cells in the arrayxe2x80x94generally includes the following steps: (a) generating a conditioning signal to remove a quantity of charge from the flash cells, which quantity of charge is related to an erase speed of the flash cell, but is insufficient to place such flash cells into an erased state; and (b) applying such conditioning signal to such flash cells while the cells are in a non-erased state. The conditioning signal is preferably applied on a global basis to the control gate while the source and drain regions are kept floating. In this fashion, the floating gate charge value is adjusted by the conditioning signal by a charge amount proportional to the original electrical field intensity. In other words, the faster cells will experience the greatest change in charge reduction. From a physical perspective, therefore, the present invention operates to substantially equalize electrical field intensities across tunnel oxides associated with each of the floating gates of the flash memory cells.
After the conditional signals treat such array, the erase speed of such fast discharge flash cells is significantly reduced. Since the other non-fast cells are left relatively unaffected, the entire distribution of erase speeds (and threshold voltages) in the cell array is equalized, so that the array can be treated with greater reliability and predictability in subsequent array operations (such as an erase operation).
Prior to performing the above conditioning, of course, a conventional programming operation can take place, followed by an additional threshold voltage measuring step. The latter measures the electrical characteristics of the flash cells to determine an expected erase discharge speed for such flash cells, and to determine which ones, if any, may need pre-erase conditioning.
During the conditioning cycle, the above steps are repeated as necessary to remove further charge from the flash cells. For each iteration, the properties of the conditioning signal, including magnitude and/or duration, can be varied to remove more or less charge from the flash cells. Usually, the cycle is set up so that each successive conditioning signal removes a greater quantity of charge.
After the array is pre-conditioned, a normal, full strength erase operation can be performed. Because the cell discharge characteristics are modified immediately in advance of the erase operation, the result is that there are fewer fast bits, and those that do exist have been slowed down to the point where it is less likely they will become over-erased.
In another embodiment of the invention, instead of a full strength erase cycle, the aforementioned conditioning cycle is instead repeated as necessary to fully erase the cells. This approach provides finer, more accurate control of the erase operation, and helps to ensure that, as the cell array characteristics change with time, the erase is performed in a manner that is tailored to such characteristics.
Thereafter, an over-erase detection operation takes place, to verify that no cells have been over-erased from said erase operation. In the event any such cells are detected, a two-stage convergence operation is preferably performed. This includes generally two independent sequential operations, including: (a) a global operation performed on the entire array; and (b) a localized operation performed only on those cells still over-erased after the global operation is completed.
In another variation of the invention, it is possible, for example, to practice the present methods in the context of a pre-program conditioning operation, so that the cell charge acquisition (instead of discharge) characteristics are modified instead. The only important consideration is that the flash cell floating gate charge values are made to substantially converge to an initial target charge value so that all of the flash cells can then be erased/programmed at an approximately uniform rate by a subsequent operation.
Another beneficial aspect of the present invention lies in the fact that characteristics of the conditioning signal can be adjusted during a manufacturing operation, so that it will be specifically tailored for the manufacturing deviations present in an associated memory array.
A novel method of erasing flash memory cells in a flash memory cell array, therefore, utilizes the aforementioned pre-erase operation in conjunction with a traditional erase operation. Again, unlike a conventional erase operation, however, the present invention can xe2x80x9cfixxe2x80x9d potentially problem cells individually for maximum control/flexibility of an erase operation. Thus, non-uniformities in electrical field intensities across tunnel oxides for flash cell in such array, caused by unpredictable but inevitable manufacturing process variations, can be substantially reduced. This results in increased product endurance, less erase time, better yields, etc.
A flash memory integrated circuit can be constructed using conventional wafer processing steps to include the teachings of the present invention. In such circuit, an array of flash memory cells is provided, each of such cells having a conduction threshold voltage, a control gate, a floating gate, a source and a drain. A logic controller circuit is coupled to the array for adjusting the threshold voltages of the cells prior to an erase operation, and is configured such that it can generate control signals in accordance with the methods described, and so that appropriate signal generating circuits can apply the aforementioned conditioning signals in the manner described above as well.
A preferred embodiment of a pre-conditioning control circuit of the present invention effectuates the above processes by the operation of: a pre-erase signal generator for generating a flash cell pre-erase signal to be applied to the flash cells; and a pre-erase signal magnitude control circuit for generating a plurality of control signals, which control signals determine a magnitude for the pre-erase signal; a pre-erase voltage supply circuit for generating a number of necessary supply voltages, including a negative voltage source in the case of a pre-erase signal; a pre-erase voltage supply switching circuit for generating a pre-erase voltage supply signal that is based on the negative voltage source; and a pre-erase voltage supply switching control circuit, which is configured to control gating of the pre-erase voltage supply switching circuit with a stepping signal. The pre-conditioning control circuit thus generates the pre-erase voltage supply signal as a function of the plurality of control signals and in a time sequence determined by the pre-erase signal magnitude control circuit. This flash cell pre-erase signal is configured, as noted earlier, to remove a quantity of charge from the flash cells in preparation for an erase operation, which quantity of charge is related to an initial erase speed of the flash cell and further being insufficient to place such flash cells into a fully erased state.
Another useful aspect of the inventive pre-conditioning control circuit includes the fact that the pre-erase signal generator includes a plurality of FETs connected in parallel, and that are activated by the plurality of control signals according to a controllable sequence so that the desired magnitude and duration of the pre-erase signal is well controlled.
As noted earlier, the control signals are varied during the time sequence so that the magnitude of said pre-erase signal is varied during said defined time sequence. In the typical case, it is increased from step to step to affect the cells morexe2x80x94i.e., to remove more and more charge during each step. Again in a preferred embodiment, a pre-erase signal is first pre-charged to a target reference voltage level before the plurality of control signals are applied, to increase speed and reliability.
To control the pre-erase voltage supply switching control circuit, a plurality of pulse generator circuits, one for each of the plurality of control signals, generate a pulsed version of such control signals that is applied and used to generate the aforementioned stepping signal.
The aforementioned pre-conditioning circuit, therefore, operates as an equalizing circuit that equalizes the erase rates of the flash cells, and thus makes it more likely that they will not be over-erased, requiring additional system overhead, loss of data from faulty bits, etc.
As alluded to earlier, the operational characteristics of the pulse generator circuits can be adjusted during a manufacturing operation, to tailor such operational characteristics to the pre-erase signal requirements of cells in a flash memory array associated with the control circuit.
Thus, a system for erasing flash memory cells in the present invention includes programmed logic within a flash controller circuit (usually a state machine), so that erase control logic includes two logical components, including: (1) a pre-erase controller circuit controlling a flash cell pre-erase operation, managing the conditioning signal magnitude, timing and sequencing, as well as (2) a conventional erase controller circuit for controlling a normal strength flash cell erase signal.
The present invention, therefore, is extremely useful in those environments that rely on FN tunneling, and helps to eliminate potential problems caused by normal process variations in tunnel oxide layers, floating gates, cell topographies, etc.